New rumors of AMD's Zen 5 & Zen 5C EPYC CPU family, codenamed Turin, have leaked out which point out up to 16 CCDs & 192 cores.
AMD To Offer Up To 192 Cores With Next-Gen EPYC CPUs: Turin With 16 Zen 5 CCDs, Turin-Dense With 12 Zen 5C CCDs & Turin-X With 1.5 GB L3 Cache
The latest rumors come from Weibo leaker, 剧毒术士马文, who seems to have acquired an internal AMD roadmap that reveals several next-generation Turin designs based on the Zen 5 and Zen 5C core architecture. Most of this information had already been talked about by Moore's Law is Dead but we get to learn a few more details such as the max cache counts and the CCD configurations.
AMD EPYC Turin & Turn-X With Zen 5: Up To 128 Cores, 4nm Process
Starting with the first family, we have the AMD EPYC Turin (Classic) which will stick with the chiplet design and house up to 128 cores, 256 threads, and TDPs of up to 500W which can be configurable on certain SKUs up to 600W (as revealed in today's Gigabyte leak). In a previous leak, it was shown that the EPYC Turin chips would feature the same L2 and L3 cache as Zen 4 with a small upgrade to the L1 cache.
Since these chips are packaged on a 4nm process node, that will lead to a smaller die area per core, allowing AMD to cram up to 16 CCDs within the same package that retains its socket compatibility with SP5 platforms.
Moving on, we have the AMD EPYC Turin-X chips which will be outfitted with a 3D V-Cache. These chips will retain the 64MB of 3D V-Cache per CCD which totals 1024 MB across the 16 CCDs & 512 MB of standard L3 cache. Totaling up to 1536 MB or 1.5 GB of L3 cache. If we combine the L2 cache which is 1 MB per core or 128 MB in total, that increases to 1664 MB of total cache which is still not including the L1 cache. That's a 33% higher cache compared to the upcoming Genoa-X CPU family.
AMD EPYC Turin Dense & Turin AI With Zen 5C: Up To 192 Cores, 3nm Process
Moving over to the Zen 5C side of things, we first have the AMD EPYC Turin Dense chips which will be succeeding Bergamo. Turin Dense isn't an official name for now but it is expected to utilize the 3nm Zen 5C cores in up to 192 core SKUs. These chips will feature up to 500W TDPs but the most interesting thing is that they are expected to hit production before the standard Turin chips. MLID states that this is due to AMD speeding things to compete directly against Intel's Sierra Forest 144 core chips which are also expected around the same time in the first half of 2024.
The overall configurations look like the following:
- AMD EPYC Turin-Classic - 16 Zen 5 CCDs / 128 Cores / 256 Threads / 512 MB L3 Cache
- AMD EPYC Turin-Dense - 12 Zen 5C CCDs / 192 Cores / 384 Threads / 384 MB L3 Cache
- AMD EPYC Turin-X 3D - 16 Zen 5 CCDs / 128 Cores / 256 Threads / 1536 MB L3 Cache
AMD's first Zen 5 CPUs are expected for next year with the company already revealed Ryzen 8000 consumer processors for a 2024 launch. The first EPYC Turin CPUs should also appear next year & we can see Dense & "X" variants in the following year.
AMD EPYC CPU Families:
| Family Name | AMD EPYC Venice | AMD EPYC Turin-Dense | AMD EPYC Turin-X | AMD EPYC Turin | AMD EPYC Siena | AMD EPYC Bergamo | AMD EPYC Genoa-X | AMD EPYC Genoa | AMD EPYC Milan-X | AMD EPYC Milan | AMD EPYC Rome | AMD EPYC Naples |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Family Branding | EPYC 11K? | EPYC 10K? | EPYC 10K? | EPYC 10K? | EPYC 8004 | EPYC 9004 | EPYC 9004 | EPYC 9004 | EPYC 7004 | EPYC 7003 | EPYC 7002 | EPYC 7001 |
| Family Launch | 2025+ | 2025? | 2025? | 2024 | 2023 | 2023 | 2023 | 2022 | 2022 | 2021 | 2019 | 2017 |
| CPU Architecture | Zen 6? | Zen 5C | Zen 5 | Zen 5 | Zen 4 | Zen 4C | Zen 4 V-Cache | Zen 4 | Zen 3 | Zen 3 | Zen 2 | Zen 1 |
| Process Node | TBD | 3nm TSMC? | 4nm TSMC | 4nm TSMC | 5nm TSMC | 4nm TSMC | 5nm TSMC | 5nm TSMC | 7nm TSMC | 7nm TSMC | 7nm TSMC | 14nm GloFo |
| Platform Name | TBD | SP5 | SP5 | SP5 / SP6 | SP6 | SP5 | SP5 | SP5 | SP3 | SP3 | SP3 | SP3 |
| Socket | TBD | LGA 6096 (SP5) | LGA 6096 (SP5) | LGA 6096 (SP5) LGA XXXX (SP6) |
LGA 4844 | LGA 6096 | LGA 6096 | LGA 6096 | LGA 4094 | LGA 4094 | LGA 4094 | LGA 4094 |
| Max Core Count | 384? | 192 | 128 | 128 | 64 | 128 | 96 | 96 | 64 | 64 | 64 | 32 |
| Max Thread Count | 768? | 384 | 256 | 256 | 128 | 256 | 192 | 192 | 128 | 128 | 128 | 64 |
| Max L3 Cache | TBD | 384 MB | 1536 MB | 384 MB | 256 MB | 256 MB | 1152 MB | 384 MB | 768 MB | 256 MB | 256 MB | 64 MB |
| Chiplet Design | TBD | 12 CCD's (1CCX per CCD) + 1 IOD | 16 CCD's (1CCX per CCD) + 1 IOD | 16 CCD's (1CCX per CCD) + 1 IOD | 8 CCD's (1CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD | 8 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (2 CCX's per CCD) + 1 IOD | 4 CCD's (2 CCX's per CCD) |
| Memory Support | TBD | DDR5-6000? | DDR5-6000? | DDR5-6000? | DDR5-5200 | DDR5-5600 | DDR5-4800 | DDR5-4800 | DDR4-3200 | DDR4-3200 | DDR4-3200 | DDR4-2666 |
| Memory Channels | TBD | 12 Channel (SP5) | 12 Channel (SP5) | 12 Channel (SP5) 6-Channel (SP6) |
6-Channel | 12 Channel | 12 Channel | 12 Channel | 8 Channel | 8 Channel | 8 Channel | 8 Channel |
| PCIe Gen Support | TBD | TBD | TBD | TBD | 96 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 4 | 128 Gen 4 | 128 Gen 4 | 64 Gen 3 |
| TDP (Max) | TBD | 480W (cTDP 600W) | 480W (cTDP 600W) | 480W (cTDP 600W) | 70-225W | 320W (cTDP 400W) | 400W | 400W | 280W | 280W | 280W | 200W |
from Wccftech https://ift.tt/WbwUtvz
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