Intel 3D Stacked CMOS Transistors Combine Backside Power & Direct Backside Contact To Deliver Increased Performance & Scaling For Next-Gen Chips

Intel is demonstrating its next-gen 3D Stacked CMOS Transistor technology which utilizes backside power & direct backside contact to deliver more performance and scaling on next-gen chips. Intel Succeeds In Large-Scale 3D Monolithic Integration of Silicon Transistors on Wafer, Demos 3D Stacked CMOS Transistors Leveraging Backside Power & Direct Backside Contact Press Release: Today, Intel unveiled technical breakthroughs that maintain a rich pipeline of innovations for the company’s future process roadmap, underscoring the continuation and evolution of Moore’s Law. At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel researchers showcased advancements in 3D stacked CMOS (complementary metal oxide semiconductor) transistors […]

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